1. Technical Field of the Invention
The present invention relates to current drivers and, more particularly, to CMOS current drivers as used, for example, in amplifier or pre-amplifier circuits.
2. Description of Related Art
Reference is now made to FIG. 1 wherein there is shown a circuit diagram of a prior art current driver 10. The current driver includes a CMOS follower stage 12 comprising an n-channel transistor 14, having a transconductance gm, whose drain is connected to Vcc (+ve or positive reference) and a p-channel transistor 16, also having a transconductance gm, whose drain is connected to Vee (−ve or negative reference). The sources of the n-channel transistor 14 and p-channel transistor 16 are connected together. The gates of the n-channel transistor 14 and p-channel transistor 16 are also connected together to receive an input signal VDC (which is generated by a circuit 30 including a set of switches producing VDC with a value of either −2.7V (or other suitable negative voltage, such as, −2.0V) or +2.7 (or other suitable positive voltage, such as, +2.0V). The connected sources of the follower stage 12 transistors are further connected to a pure resistor R through which a current IDC (the DC driver current) flows toward a node 18. Connected between Vcc and node 18 is a first current source 20. A second current source 22 is connected between the node 18 and Vee. These current sources assist in the generation of current IOS which is the initial peak overshoot (OS) current. The IOS current exceeds in magnitude the settled DC current IDC of the driver. An output 24, at which an output voltage HW appears, is connected to node 18. The output current IW at output 24 is equal to the sum of the current IDC (provided from the resistor R) and the current IOS (provided by the first current source 20). The impedance Zout at the output 24 of the driver 10 is equal to the sum of the resistance value for the resistor R plus the value 1/gm for the driver transistor of the follower stage 12 when that transistor is on.
In many applications for the current driver 10, the illustrated circuit is only one-half of the overall current driver and a symmetrical circuit to that illustrated is also provided. In this configuration, while one current driver 10 is sourcing current, its partner current driver is sinking that current. Circuit configurations of this type are well known to those skilled in the art.
This current driver 10 implementation suffers from a number of drawbacks including speed limitations, safe operating area problems and wasted current during overshoot (OS) problems. There is accordingly a need for an improved circuit implementation for the current driver which addresses some or all of these problems, as well as other problems recognized by those skilled in the art.